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Ordering number : ENA1642
CMOS IC
LV51144T
Overview
1-Cell Lithium-Ion Battery Protection IC
The LV51144T is protection IC for rechargeable Li-ion battery by high withstand voltage CMOS process. The LV51144T protect single-cell Li-ion battery from over-charge, over-discharge, charge over-current and discharge over-current.
Features
* High accuracy detection voltage Over-charge detection(no hysteresis) Over-discharge detection(no hysteresis) Charge over-current detection Discharge over-current detection Operation Over-discharge condition 25mV 25% 30mV 20mV
* Delay time (internal adjustment) * Low current consumption
Typ. 3.0A Max. 0.1A
* 0V cell battery charging function * The over-discharge detection is released only when the charger is connected.
Specifications
Absolute Maximum Ratings
Parameter Supply voltage Input voltage of VM Output voltage of CO Output voltage of DO Power dissipation Operating temperature Storage temperature Symbol VDD VM VCO VDO PD Topr Tstg Conditions Ratings VSS-0.3 to VSS+7 VDD-28 to VDD+0.3 VM-0.3 to VDD+0.3 VSS-0.3 to VDD+0.3 350 -40 to +85 -55 to +125 Unit V V V V mW C C
Any and all SANYO Semiconductor Co.,Ltd. products described or contained herein are, with regard to "standard application", intended for the use as general electronics equipment (home appliances, AV equipment, communication device, office equipment, industrial equipment etc.). The products mentioned herein shall not be intended for use for any "special application" (medical equipment whose purpose is to sustain life, aerospace instrument, nuclear control device, burning appliances, transportation machine, traffic signal system, safety equipment etc.) that shall require extremely high level of reliability and can directly threaten human lives in case of failure or malfunction of the product or may cause harm to human bodies, nor shall they grant any guarantee thereof. If you should intend to use our products for applications outside the standard applications of our customer who is considering such use and/or outside the scope of our intended standard applications, please consult with us prior to the intended use. If there is no consultation or inquiry before the intended use, our customer shall be solely responsible for the use. Specifications of any and all SANYO Semiconductor Co.,Ltd. products described or contained herein stipulate the performance, characteristics, and functions of the described products in the independent state, and are not guarantees of the performance, characteristics, and functions of the described products as mounted in the customer's products or equipment. To verify symptoms and states that cannot be evaluated in an independent device, the customer should always evaluate and test devices mounted in the customer's products or equipment.
D2409 SY 20091221-S00005 No.A1642-1/13
LV51144T
Electrical Characteristics at Topr = 25C, unless otherwise specified
Parameter Detection voltage Over-charge detection voltage Over-discharge detection voltage (*2) Charge over-current detection voltage Discharge over-current detection voltage Load short-circuiting detection voltage Input voltage Input voltage between VDD and VSS 0V battery charge starting charger voltage Current consumption Current consumption on operation Current consumption on shutdown Output resistance CO : Pch ON resistance CO : Nch ON resistance DO : Pch ON resistance DO : Nch ON resistance Discharge over-current release resistance Detection delay time Over-charge detection delay time tc VDD = VC-0.2VVC+0.2V, VM = 0V VDD = Vdc+0.2VVdc-0.2V, VM = 0V Charge over-current detection delay time Discharge over-current detection delay time Load short-circuiting detection delay time Release delay time Release delay time 1 Over-discharge release Charge over-current release (*1) Discharge over-current release Load short-circuiting release Release delay time 2 Over-charge release trel2 VDD = VC+0.2VVC-0.2V, VM = 1.0V 6 8.0 16.0 24.0 ms trel1 6 1.0 2.0 3.0 ms tic tidc tshort VDD = 3.0V, VM = 0V-1.0V VDD = 3.0V, VM = 0V1.0V VDD = 3.0V, VM = 0V3.0V 6 6 6 5.6 5.6 190 8.0 8.0 370 10.4 10.4 550 ms ms s 6 0.70 1.0 1.30 s Rcop CO = 3.0V, VDD = 3.5V, VM = 0V CO = 0.5V, VDD = 4.6V, VM = 0V DO = 3.0V, VDD = 3.5V, VM = 0V DO = 0.5V, VDD = VM = 1.8V VDD = 3.5V, VM = 1.0V 5 1.5 3.0 4.5 k Iopr Isdn VDD = 3.5V, VM = 0V VDD = VM = 1.8V 4 4 3.0 6.0 0.1 A A VDD Vcha Internal circuit operating voltage Acceptable 3 1.8 0.9 7.0 1.4 V V VC Vdc VIc VIdc Vshort Based on VDD, VDD = 3.5V 1 1 2 2 2 3.625 2.438 -0.230 0.180 -1.7 3.650 2.500 -0.200 0.200 -1.3 3.675 2.563 -0.170 0.220 -1.0 V V V V V Symbol Conditions Test circuit min Ratings typ max Unit
Rcon
5
0.5
1.0
1.5
k
Rdop
5
1.7
3.5
5.0
k
Rdon Rdwn
5 5
1.7 15.0
3.5 30.0
5.0 60.0
k k
Over-discharge detection delay time
tdc
6
21.7
31.0
40.3
ms
Note :*1 When the charger is connected under over-discharge , this means the time after the over-discharge detection is released. *2 The over-discharge detection is released at this voltage only when the charger is connected. The over-discharge detection isn't released if the charger isn't connected.
No.A1642-2/13
LV51144T
Package Dimensions
unit : mm (typ) 3356
0.4
Pd max -- Ta
Specified board : 33x5x1.0mm3 glass epoxy 0.35 (Both sides substrate)
2.9 6
Allowable power dissipation, Pd max - W
0.3
1.6
2.8
0.2
0.4
0.14 0.1
1 (0.5)
2 0.95 0.4
0.15
1.3 MAX
(1.2)
0 - 40
0
40
80
120
0.8
Ambient temperature, Ta - C
0.05
SANYO : SOT-23-6
Pin Assignment
VSS 6 VDD 5 NC 4
Top view 1 DO 2 VM 3 CO
Pin Function
Pin No. 1 2 3 4 5 6 Pin Name DO VM CO NC VDD VSS Description FET gate connection for discharge control (CMOS output) Voltage monitoring for charger negative FET gate connection for charge control (CMOS output) N/C Positive power input Negative power input
No.A1642-3/13
LV51144T
Block Diagram
Oscillator Counter VDD Control Circuit Short Detector + VM Level Shifter CO
+ Over-charge Detector
Charge Over-current Detector
+ Over-discharge Detector VSS Discharge Over-current Detector
+ -
DO
Measurement Conditions
* Over-charge detection voltage --- [Circuit 1] Set V1 = 3.0V and V2 = 0V. Over-charge detection voltage VC is V1 at which VCO goes "Low" from "High" when V1 is gradually increased from 3.0V. Then IC is released from the over-charge state and VCO goes "High" from "Low" at the voltage "Measured VC" when V1 is gradually decreased. * Over-discharge detection voltage --- [Circuit 1] Set V1 = 3.0V and V2 = 0V. Over-discharge detection voltage Vdc is V1 at which VDO goes "Low" from "High" when V1 is gradually decreased from 3.0V. Next, set V2 under to charge over-current detection voltage VIc. Then IC is released from the over-discharge state at Vdc and VDO goes "High" from "Low". * Charge over-current detection voltage --- [Circuit 2] Set V1 = 3.0V and V2 = 0V. Charge over-current detection voltage VIc is V2 at which VCO goes "Low" from "High" when V2 is gradually decreased from 0V. * Discharge over-current detection voltage --- [Circuit 2] Set V1 = 3.0V and V2 = 0V. Discharge over-current detection voltage VIdc is V2 at which VDO goes "Low" from "High" when V2 is gradually increased from 0V. * Load short-circuiting detection voltage --- [Circuit 2] Set V1 = 3.0V and V2 = 0V. Load short-circuiting detection voltage Vshort is V2 at which VDO goes "Low" from "High" within a time between the minimum and the maximum value of load short-circuiting detection delay time tshort, when V2 is increased rapidly within 10s. * 0V battery charge starting charger voltage --- [Circuit 3] Set V1 = V2 = 0V and decrease V2 gradually. 0V battery charge starting charger voltage Vcha is V2 when VCO goes "High" (V1-0.1V or higher).
Continued on next page.
No.A1642-4/13
LV51144T
Continued from preceding page.
* Current consumption on operation and shutdown --- [Circuit 4] Set V1 = 3.5V and V2 = 0V on normal condition. IDD shows current consumption on operation Iopr. Set V1 = V2 = 1.8V on over-discharge condition. IDD shows current consumption on shutdown Isdn. * Co : Pch ON resistance, Co : Nch ON resistance --- [Circuit 5] Set V1 = 3.5V, V2 = 0V and V3 = 3.0V. (V1-V3)/|ICo| is Pch ON resistance Rcop. Set V1 = 4.6V, V2 = 0V and V3 = 0.5V. V3/|ICo| is Nch ON resistance Rcon. * Do : Pch ON resistance, Do : Nch ON resistance --- [Circuit 5] Set V1 = 3.5V, V2 = 0V and V4 = 3.0V. (V1-V4)/|IDo| is Pch ON resistance Rdop. Set V1 = V2 = 1.8V and V4 = 0.5V. V4/|IDo| is Nch ON resistance Rdon. * Discharge over-current release resistance --- [Circuit 5] Set V1 = 3.5V, V2 = 0V at first. And then, set V2 = 1.0V. V2/|IVM| is discharge over-current release resistance Rdwn. * Over-charge detection delay time, Release delay time 2 --- [Circuit 6] Set V2 = 0V. Increase V1 from the voltage VC-0.2V to VC+0.2V rapidly within 10s. Over-charge detection delay time tc is the time needed for VCO to go "Low" just after the change of V1. Next, set V2 = 1V and decrease V1 from VC+0.2V to VC-0.2V rapidly within 10s. Over-charge release delay time trel 2 is the time needed for VCO to go "High" just after the change of V1. * Over-discharge detection delay time, Release delay time 1 --- [Circuit 6] Set V2 = 0V. Decrease V1 from the voltage Vdc+0.2V to Vdc-0.2V rapidly within 10s. Over-discharge detection delay time tdc is the time needed for VDO to go "Low" just after the change of V1. Next, set V2 = -1V and increase V1 from Vdc-0.2V to Vdc+0.2V rapidly within 10s. Release delay time 1 trel1 in case of over-discharge is the time needed for VDO to go "High" just after the change of V1. * Charge over-current detection delay time, Release delay time 1 --- [Circuit 6] Set V1 = 3.0V and V2 = 0V. Decrease V2 from 0V to -1V rapidly within 10s. Charge over-current delay time tic is the time needed for VCO to go "Low" just after the change of V2. Next, increase V2 from -1V to 0V rapidly within 10s. Release delay time 1 trel1 in case of charge over-current is the time needed for VCO to go "High" just after the change of V2. * Discharge over-current detection delay time, Release delay time 1 --- [Circuit 6] Set V1 = 3.0V and V2 = 0V. Increase V2 from 0V to 1V rapidly within 10s. Discharge over-current delay time tidc is the time needed for VDO to go "Low" just after the change of V2. Next, decrease V2 from 1V to 0V rapidly within 10s. Release delay time 1 trel1 in case of discharge over-current is the time needed for VDO to go "High" just after the change of V2. * Load short-circuiting detection delay time, Release delay time 1 --- [Circuit 6] Set V1 = 3.0V and V2 = 0V. Increase V2 from 0V to 3.0V rapidly within 10s. Load short-circuiting detection delay time tshort is the time needed for VDO to go "Low" just after the change of V2. Next, decrease V2 from 3.0V to 0V rapidly within 10s. Release delay time 1 trel1 in case of load short-circuiting is the time needed for VDO to go "High" just after the change of V2.
No.A1642-5/13
LV51144T
Measurement Circuits
* Circuit 1 * Circuit 2
330 VDD 0.1F V1 VSS DO CO V2 VDO V V VCO VDO V V VCO VDD 0.1F VM V1=3.5V VSS DO CO V2
LV51144 LV51140
LV51144 LV51140
VM
* Circuit 3
* Circuit 4
IDD VDD 0.1F V1 VSS DO CO V2 VCO 10M V A VDD
LV51144 LV51140
0.1F VM V1 VSS
LV51144 LV51140
DO CO
VM
V2
* Circuit 5
* Circuit 6
VDD 0.1F V1 VSS DO CO A IDO A A ICO IVM
VDD
LV51144 LV51140
VM
V1
LV51144 LV51140
VSS DO CO
VM
V2 VDO TM TM VCO
V4
V3
V2
TM = Time Measurement
No.A1642-6/13
LV51144T
Application Circuit Example
R1
VDD C1 Battery VSS Do Co VM
LLV51144 V51140T
R2
C2
External Components
Items Resistor 1 Capacitor 1 Resistor 2 Symbol R1 C1, 2 R2 Recommended value 330 0.1F 3.9k
* The supply voltage (VDD) to this IC is stabilized by R1 and C1. Moreover, R1 and R2 act as the current restriction resistances at the time of reverse-connecting a charger, or at the time of connecting a charger which outputs the voltage exceeding the absolute maximum rating of this IC. Be sure to connect these components. * If the value of R1 is too large, the over-charge detection voltage will become high due to the current consumption of this IC. 330 is recommended. * If the value of C1 is too small, this IC may be in a shutdown state at the time of the discharge over-current or the load short-circuiting. 0.1F is recommended. * Use the value within the limits shown in the table about the value of R2. In order to reduce the current at the time of reverse-connecting a charger, we recommend to choose R1 and R2 so that the sum total of resistance values is more than 4k. The recommended value of R2 is 3.9k. Note 1 : The connection diagram and each value of external components shown above are just recommendation. Including a battery and FETs, determine the circuit after sufficient evaluation about your actual application. These numbers don't mean to guarantee the characteristic of the IC. Note 2 : The IC is susceptible to static electricity and some pins are easily damaged by it. Handle the IC carefully.
No.A1642-7/13
LV51144T
Description of Operation
* Normal condition This IC monitors the battery voltage (VDD) and the voltage of VM terminal, and controls charge and discharge. If the battery voltage (VDD) is in the range from the over-discharge detection voltage (Vdc) to the over-charge detection voltage (VC) and the VM terminal voltage is in the range from the charge over-current detection voltage (VIc) to the discharge over-current detection voltage (VIdc), this IC turns on both the charge and discharge control FETs. This state is called the normal condition, and charge and discharge are possible together. * Discharge over-current detection, Load short-circuiting detection When the discharge current becomes equal to or higher than the specified value under the normal condition, and if the VM terminal voltage is in the range from the discharge over current detection voltage (VIdc) to the short-circuiting detection voltage (Vshort) and that state is maintained during more than the discharge over-current detection delay time (tidc), this IC turns off the discharge control FET to stop discharge. This state is called the discharge over-current condition. At that time, if the VM terminal voltage is equal to or higher than Vshort and that state is maintained during more than the load short-circuiting detection delay time (tshort), this IC turns off the discharge control FET to stop discharge. This state is called the load short-circuiting detection condition. While load is connected, in both conditions, the VM terminal voltage equals to VDD potential due to the load, but it falls by the discharge over-current release resistance (Rdwn) when the load is removed and the resistance between (+) and (-) terminals of battery pack (refer to "Application Circuit Example") becomes larger than the value which enables the automatic return. Then the VM terminal voltage becomes less than VIdc, and if that state is maintained during more than the release delay time 1 (trel1), this IC returns to normal condition. Note : The resistance value between (+) and (-) terminals of battery pack for automatic return changes with battery voltage (VDD) or VIdc. The standard is expressed with the following equation. Resistance value for automatic return = Rdwn x (VDD / VIdc - 1) * Charge over-current detection When the charge current becomes equal to or higher than the specified value under the normal condition, if the VM terminal voltage becomes less than the charge over-current detection voltage (VIc) and that state is maintained during more than the charge over-current detection delay time (tic), this IC turns off the charge control FET to stop charge. This state is called the charge over-current detection condition. Then the VM terminal voltage becomes equals to or higher than VIc and that state is maintained during more than the release delay time 1 (trel1) when the charger is removed and the load is connected, this IC returns to the normal condition.
* Over-charge detection When the battery voltage (VDD) under the normal condition becomes equal to or higher than the over-charge detection voltage (VC) and that state is maintained during more than the over-charge detection delay time (tc), this IC turns off the charge control FET and stops charge. This state is called the over-charge detection condition. Release from the over-charge detection condition includes following three cases. (1) When VDD falls to Vc without load and that state is maintained during more than the delay time 2 (trel2), this IC turns on the charge control FET and returns to the normal condition. (2) When the load is installed and discharge starts, the discharge current flows through the internal parasitic diode of the charge control FET. Then the VM terminal voltage rises to only the Vf voltage of the internal parasitic diode from VSS potential. At this time, if the VM terminal voltage is higher than the discharge over-current detection voltage (VIdc) and VDD is equal to or less than VC, this IC returns to the normal condition when this state continues more than the delay time 2 (trel2). (3) In case (2), if the VM terminal voltage is higher than the discharge over-current detection voltage (VIdc) and VDD is equal to or higher than VC, battery is discharged until VDD becomes less than VC, and then this IC returns to the normal condition when this state continues more than the delay time 2 (trel2).
No.A1642-8/13
LV51144T
* Over-discharge detection When the battery voltage (VDD) under the normal condition becomes equal to or less than the over-discharge detection voltage (Vdc) and that state continues for more than the over-discharge detection time (tdc), this IC turns off the discharge control FET and stops discharging. This state is called the over-discharge detection condition. Recovery from the over-discharge detection condition is achieved only by connecting the charger. * Return from over-discharge When the charger is connected and charging starts, the charge current flows through the internal parasitic diode of the discharge control FET. When VDD becomes higher than Vdc and that state continues for more than the delay time 1(trel1), this IC is released from the over-discharge detection condition automatically and returns to the normal condition. If VDD is less than Vdc, this IC returns to the normal condition when VDD becomes equal to or higher than Vdc, and this state continues more than delay time 1 (trel1). This IC stops all internal circuits (Shutdown condition) after detecting the over-discharge and reduces current consumption. (Max 0.1A, at VDD = 1.8V) * Charge to 0V battery (1) 0V battery charge function If the voltage of charger (the voltage between VDD and VM) is larger than the 0V battery charge starting charger voltage (Vcha), 0V battery charge becomes possible when CO terminal outputs VDD terminal potential and turns on the charge control FET.
No.A1642-9/13
LV51144T
Timing Chart
* Discharge over-current detection, Load short-circuiting detection, Charge over-current detection
Load connected Load connected Charger connected Load connected
VC VDD
Vdc
VDD Vshort VM Vldc VSS Vlc
VDD DO
VSS
VDD CO
VSS VM
tidc trel1
tshort trel1
tic trel1
VC Vdc VIc VIdc Vshort
: Over-charge detection voltage : Over-discharge detection voltage : Charge over-current detection voltage : Discharge over-current detection voltage : Load short-circuiting detection voltage
tic tidc tshort trel1
: Charge over-current detection delay time : Discharge over-current detection delay time : Load short-circuiting detection delay time : Release delay time 1
No.A1642-10/13
LV51144T
* Over-charge detection
Charger connected Charger connected Load connected
VC VDD Vdc
VM
VIdc VSS
VDD DO VSS VDD CO VSS VM
tc
trel2
tc trel2
VC : Over-charge detection voltage Vdc : Over-discharge detection voltage Vidc : Discharge over-current detection voltage
tc : Over-charge detection delay time trel2 : Release delay time 2
No.A1642-11/13
LV51144T
* Over-discharge detection
VRdc
VC : Over-charge detection voltage Vdc : Over-discharge detection voltage VRdc : Over-discharge return voltage Vic : Charge over-current detection voltage Vidc : Discharge over-current detection voltage
tdc : Over-discharge detection delay time trel1 : Release delay time 1
No.A1642-12/13
LV51144T
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This catalog provides information as of December, 2009. Specifications and information herein are subject to change without notice. PS No.A1642-13/13

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